LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY addbuff2 IS
   PORT(
       TABLE_READY: IN STD_LOGIC; -- TBL_to_FWD_ACK
       CLOCK :  IN STD_LOGIC;     -- clk
       portChoice : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- portChoice
       portvalid: IN STD_LOGIC; -- portReady
	   des_mux0, des_mux1,des_mux2,des_mux3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- desAddress0
	   src_mux0, src_mux1,src_mux2,src_mux3: IN STD_LOGIC_VECTOR(7 DOWNTO 0);  -- srcAddress0
	   WE_READY: OUT STD_LOGIC; -- ACK to table indicating that table can start reading the data
	   src_ready0, src_ready1, src_ready2, src_ready3 : IN STD_LOGIC; -- sendingsrcAddress0
	   des_ready0, des_ready1, des_ready2, des_ready3 : IN STD_LOGIC; -- sendingdesAddress0
	   srcPort : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);	  -- FWD_to_TBL_srcPort
	   srcAddress : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);-- FWD_to_TBL_srcAddress
	   desAddress : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) -- FWD_to_TBL_desAddress
       );
END addbuff2;

ARCHITECTURE structural OF addbuff2 IS
COMPONENT Dff1 IS
   PORT(
        D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
       ENABLE: IN STD_LOGIC;
       count :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       CLOCK :  IN STD_LOGIC;
	   Q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
       );
END COMPONENT;
COMPONENT counter IS
	PORT
	(
		clock		: IN STD_LOGIC ;
		sclr		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
END COMPONENT;
COMPONENT AddressMUX IS
   PORT(
       CLOCK :  IN STD_LOGIC;
       portChoice : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	   src_mux0, src_mux1,src_mux2,src_mux3  : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	   des_mux0, des_mux1,des_mux2,des_mux3 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	   src_ready0, src_ready1, src_ready2, src_ready3 : IN STD_LOGIC; 
	   des_ready0, des_ready1, des_ready2, des_ready3 : IN STD_LOGIC;
	   src_ready: OUT STD_LOGIC;
	   des_ready: OUT STD_LOGIC;
	   srcAddress : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	   desAddress : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
       );
END COMPONENT;




SIGNAL S1,S2,S3,S4,S5,S6:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL D1,D2,D3,D4,D5,D6:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL sclr,src_ready,des_ready:STD_LOGIC;
SIGNAL count:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL sa,da:STD_LOGIC_VECTOR(7 DOWNTO 0);
--SIGNAL done1,done2:STD_LOGIC;

BEGIN
MUX22: AddressMUX Port map(CLOCK,portChoice,src_mux0, src_mux1,src_mux2,src_mux3,des_mux0, des_mux1,des_mux2,des_mux3,src_ready0, src_ready1, src_ready2, src_ready3,des_ready0, des_ready1, des_ready2, des_ready3,src_ready,des_ready,sa,da );
counter11: counter port map(CLOCK,sclr or (src_ready nor des_ready) ,count);

Df1:Dff1 PORT MAP(sa,src_ready ,count,CLOCK,S1);
srcAddress(47 DOWNTO 40)<=S1;
Df11:Dff1 PORT MAP(da,des_ready, count,CLOCK,D1);
desAddress(47 DOWNTO 40)<=D1;
Df2:Dff1 PORT MAP(S1,src_ready, count,CLOCK,S2);
srcAddress(39 DOWNTO 32)<=S2;
Df21:Dff1 PORT MAP(D1,des_ready,count,CLOCK,D2);
desAddress(39 DOWNTO 32)<=D2;
Df3:Dff1 PORT MAP(S2,src_ready, count,CLOCK,S3);
srcAddress(31 DOWNTO 24)<=S3;
Df31:Dff1 PORT MAP(D2,des_ready , count,CLOCK,D3);
desAddress(31 DOWNTO 24)<=D3;
Df4:Dff1 PORT MAP(S3,src_ready , count,CLOCK,S4);
srcAddress(23 DOWNTO 16)<=S4;
Df41:Dff1 PORT MAP(D3,des_ready , count,CLOCK,D4);
desAddress(23 DOWNTO 16)<=D4;
Df5:Dff1 PORT MAP(S4,src_ready, count,CLOCK,S5);
srcAddress(15 DOWNTO 8)<=S5;
Df51:Dff1 PORT MAP(D4,des_ready , count,CLOCK,D5);
desAddress(15 DOWNTO 8)<=D5;
Df6:Dff1 PORT MAP(S5,src_ready ,count,CLOCK,S6);
srcAddress(7 DOWNTO 0)<=S6;
Df61:Dff1 PORT MAP(D5,des_ready,count,CLOCK,D6);
desAddress(7 DOWNTO 0)<=D6;



PROCESS(TABLE_READY,count,portvalid,portChoice,src_ready,des_ready)
BEGIN
srcPort<=portChoice;
if(count="1100" and TABLE_READY<='1' and portvalid<='1'  ) then
 WE_READY<='1';
sclr<='1';
else
WE_READY<='0';
sclr<='0';
end if;
END PROCESS;
END structural;


